TSMC's CoWoS capacity in 2028: 260,000 wafers and who gets them

• 260kCoWoS wafers a month TSMC targets for 2028, against roughly 130k at the end of 2026
• 60%of that output goes to Nvidia, on the allocation a back-end supply-chain veteran describes
• ~70%TGV copper-fill yield he sees, against a street range of 75–85%

TSMC's CoWoS capacity is running at roughly 130,000 wafers a month as 2026 closes. The street's figure for 2028 is 260,000, Yole publishes nearer 270,000, and a packaging supply-chain veteran who has sold process equipment into TSMC's back end for two decades puts 260,000 inside the achievable range, on the ground that every milestone on the way to it has moved earlier rather than later.

The allocation behind that number is more useful than the number itself, because packaging is the last hard gate before an accelerator ships. Nvidia takes about 60% of output, Broadcom 15%, AMD 10%, Marvell 6%, AWS and the other AI chip customers 5%, MediaTek 2%, and everyone else 3%. Converted into wafers, that is the closest thing to a public forecast of 2028 accelerator volumes that does not come out of a sell-side model. One caveat travels with it: there is no industry standard for what counts as capacity, so the split is directionally right rather than precise.

The split, in wafers

What sets the ceiling

Not floor space, and not the number of tools installed. Capacity is defined by the single tightest station in the process flow, which today is bonding with hybrid bonding next, and a new back-end fab runs about three years from groundbreaking to full ramp — longer than a leading-edge front-end fab, because the hard part sits at the back of the process rather than the front. Two sites with similar published plans can therefore have very different real ceilings.

All of the incremental capacity is CoWoS-L, the organic-substrate version that pairs redistribution layers with local silicon bridges, carries twelve HBM stacks for HBM4 and takes die larger than reticle. It is also harder: more redistribution layers, finer lines, and a mismatch in thermal expansion between silicon and the organic build-up that produces warpage.

The step that sets the date

TSMC's panel-level successor, CoPoS, is widely expected to reach volume in 2027 or 2028. The people tracking it most closely treat 2029 as the reference date, because the through-glass via metallization — specifically copper fill — yields around 70% against a street range of 75% to 85%, and that gap is the whole schedule. CoPoS is not a retrofit of a CoWoS line either: TGV, metallization and fill all need new tools, which means a new building rather than a new module.

Why panel-level packaging exists

Area. On a 300mm wafer a 75x75 die uses 48% of the area at best, against more than 84% on a 310x310 glass or silicon panel, and the die count goes from 6 to 16. Above 75x75, CoWoS stops fitting. That ratio, not any shortage of silicon, is why the industry is building it — and why CoPoS does not compete with CoWoS for capacity, since the two share almost no process steps.

This page is the public data companion to The Call 01 in Two Tides. The conversation itself, edited and with the source's own corrections left in, is the post in the letter.